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TorchTPU: Running PyTorch Natively on TPUs at Google Scale
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The challenges of building for modern AI infrastructure have fundamentally shifted.
Key facts
- By maximizing TensorCore utilization and minimizing memory bandwidth overhead, Fused Eager consistently delivers a 50% to 100+% performance increase over Strict Eager, with no setup required
- For example, they frequently see models hardcoding attention head dimensions to 64, while current-generation TPUs achieve peak matrix multiplication efficiency at dimensions of 128 or 256
- Today, TorchTPU supports Distributed Data Parallel (DDP), Fully Sharded Data Parallel v2 (FSDPv2), and PyTorch’s DTensor out of the box
- Their translation layer maps PyTorch's operators directly into StableHLO, XLA’s primary Intermediate Representation (IR) for tensor math
Summary
At Google, their Tensor Processing Units (TPUs) are foundational to their supercomputing infrastructure. As an engineering team, their mandate was to build a stack that leads with usability, portability, and excellent performance. To understand TorchTPU, you first have to understand the hardware it targets. A TPU system is not a chip; it is an integrated network. A host is attached to multiple chips, and each chip connects to the host and to other chips via their Inter-Chip Interconnect (ICI).