China · Intel · TSMC · AMD · Tom's Hardware
The current state of Hybrid Bonding in 2026, TSMC sits at 6 microns and the HBM delay that nobody expected
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Hybrid bonding, the copper-to-copper joining technique that replaces solder microbumps in 3D chip stacks, is in high-volume production on logic chips and has been postponed for use with memory.
Key facts
- SK hynix is investing $3.87 billion in an advanced-packaging plant in Indiana, with production targeted for 2028, and Micron broke ground on a $7 billion HBM advanced-packaging facility in Singapore
- AMD has cited roughly 15 times the interconnect density of conventional 2.5D microbump stacking, and figures presented at TSMC's 2026 technology symposium put face-to-face hybrid bonding
- That changed back in January when JEDEC raised the HBM package height limit from 720 to 775 microns, and the extra room means 16-high HBM4 stacks can be assembled with microbumps after all
- Applied Materials and Besi cite around 1,600 die placements per hour on the Kinex platform, and Besi's Chameo bonders are rated near 2,000 chips per hour, with the next generation aiming
Summary
The technique works by polishing two dies flat, then bonding their copper pads and surrounding dielectric directly under heat and pressure, with no solder bump in between. Microbumps have historically run at pitches around 40 microns, tightening toward 10 for the latest memory. The method is split into two different approaches: wafer-to-wafer and die-to-wafer. In contrast, die-to-wafer bonding places individual, pre-tested dies onto a wafer, which is what chiplet and HBM stacks require, because it allows known-good-die selection and the mixing of different die sizes and process nodes.