Compute · Samsung · chipsandcheese.com
Xcena and Samsung's Near Memory Compute CXL Device
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Memory expansion has been attractive for years, and is more relevant than ever because ML models have an insatiable appetite for memory capacity.
Key facts
- The reporter is confused because a 1024 entry map cache only covers 64 MB with 64 KB pages, but XCENA’s documentation suggests the cache defaults to 16 GB and has adjustable capacity in 16 MB steps
- For perspective, an Nvidia GeForce GTX 1080 with similar onboard memory bandwidth has 8.8 TFLOPS of FP32 compute, compared to the 3 TFLOPS available from the MX1
- On the memory expansion front, the MX1 can host up to 2 TB of DDR5 memory and connects to the host via a PCIe 6/CXL 3.2 x8 interface
- XCENA’s site gives an example with 115.5 GB of pinned memory, out of 231 GB of attached DRAM
Summary
On the memory expansion front, the MX1 can host up to 2 TB of DDR5 memory and connects to the host via a PCIe 6/CXL 3.2 x8 interface. The MX1 therefore has 128 GB/s of bandwidth to the host, or 64 GB/s in each direction. MX1’s chip hosts 3072 RISC-V cores, divided into clusters of 32 cores that share L2 caches and a data TLB. The MX1 is fabricated using Samsung’s 4nm process and consumes 40 W, implying that each each RISC-V core draws a bit under 13 mW. XCENA uses a lot of small cores because they’re targeting data-parallel workloads, where single threaded performance is less important than utilizing high memory bandwidth while maximizing power efficiency. Each RISC-V core uses in-order execution and runs at a pedestrian 1.1 GHz.