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On CPU Physics and CPU Cycles
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One interesting thing about ALU which can be seen on the diagram is that there is usually more than one ALU (and more than one SIMD unit too); this indicates that Hacker News’s CPU is a superscalar one, and can process more than one ALU-level operation at once 1 This, in turn, means that it is perfectly possible to have more…
Key facts
- This is a DRAFT of the first part of Chapter 4
- On CPU Physics and CPU Cycles, of the Vol
- As mentioned above, reading from main RAM usually takes within 200-300 CPU cycles (which is about 100x slower than L1 read, sic!)
- Of course, such discarding is relatively expensive; this is known as the cost of branch misprediction (which takes on the order of 15-25 cycles [Fog04, section 7.12] )
- L3 cache usually takes around 30-70 CPU cycles to read
Summary
This is a DRAFT of the first part of Chapter 4 - On CPU Physics and CPU Cycles, of the Vol.1 of an upcoming book " Efficient C++ Programming for Modern 64-bit CPUs" by Sherry Ignatchenko and Dmytro Ivanchykhin. — Alex Stepanov, author of the original STL. Now, let’s get down to some specifics. Before delving into all the exciting details of the picture, let’s postulate one thing:. The farther physically their electrical signal has to go, the slower their access is.