Nvidia · Google · Intel · TSMC · Amazon · Semiconductor · Tom's Hardware
Google reportedly books Intel for packaging more than 3 million TPUs in 2028
Compiled by KHAO Editorial — aggregated from 1 source. See llms.txt for citation guidance.
◌ Single Source
Google has placed an order for Intel to build more than 3 million of its TPUs in 2028 after months of testing Intel's advanced packaging, citing four people familiar with the matter.
Key facts
- Intel Foundry lost $10.3 billion on $17.8 billion of revenue in 2025, and in Q1 2026, the division posted $5.4 billion in revenue against a $2.4 billion operating loss, with external customers
- Bernstein analysts estimate EMIB packaging costs a few hundred dollars per chip against $900 to $1,000 for CoWoS on a Rubin-class processor, though the firm flags the fact that there’s a “ lack
- Nvidia is naturally expected to account for most global CoWoS demand, about 60% this year, with Broadcom and AMD absorbing another 26% between them, leaving custom-ASIC designers and smaller AI-chip
- Intel cites package utilization near 90% EMIB against roughly 60% for interposer-class packaging, because small bridges tile efficiently while large interposers don’t
Summary
Specifically, SK hynix needs to know whether Intel can run packaging to the standard that AI accelerators demand. This isn’t a first for Intel: Google and Amazon were reported to be in active discussions for their custom AI processors back in April, but the remarks from these sources move those “discussions” to a solid unit figure and production timeline, adding in SK hynix qualification that would ultimately determine whether any of it reaches Nvidia accelerators. TSMC's leading-edge wafer lines and its CoWoS packaging are both at capacity. The queue for CoWoS is concentrated across a handful of buyers.